A substrate wafer with a single crystal thin film formed by epitaxial growth is generally called an epitaxial wafer. Crystal growth is carried out on the substrate by vapor phase epitaxial deposition, and the growth is carried out by aligning with the lowest crystal plane of the substrate. Epitaxial silicon wafers are widely used in diodes, IGBT power devices, low-power digital and analog integrated circuits, and mobile computing and communication chips. CETC also provides different types of production grade doped epitaxial wafers, N-type or P-type, etc. according to customer requirements.

The 300mm polished wafer is a wafer of high-purity silicon. After the monocrystalline silicon ingot is produced, the cylindrical monocrystalline silicon from the ingot is cut into thin slices. It is usually widely used in power devices, digital and analog integrated circuits and memory chips. CETC also accepts different conditions from customers and manufactures high-quality production grade silicon wafers that meet customer needs.
• Growth method: Cz
• Diameter: 300mm
• Crystal orientation: <100>±1°
• P type dopants: Boron
• Resistivity: 0.015Ω·cm~100Ω·cm
• Thickness: 775±25µm
• TTV: ≤0.9µm
• Warp: ≤25µm
• Bow: ≤10µm
• Notch: As per SEMI Standard
• Notch depth: 1.0+0.25mm/-0.00mm
• Notch angle: 90°+5°/-1°
• Notch orientation: <110>±1°
• Front surface: Polished
• Back surface: Polished
• Frontside particles ≥0.09µm (LPD/COP): ≤15no./wafer
• Edge exclusion: 3.0mm
• Lasermark: SEMI Standard Backside T7 and M12
• Applicable Surface Metals Al, Ca, Cl, Cr, Cu, Fe, K, Na, Ni, Zn: ≤1¹⁰atoms/cm²

Test Wafer is mainly used for experiments and inspections. In the early stage of FAB manufacturing equipment being put into use, Test wafer is also widely used to improve the stability of the equipment. Reconstituted wafers are commonly used in test wafers because the purpose of use is different from that of the conventional wafers.

• Growth method: Cz, MCz
• Diameter: 150mm, 200mm
• Crystal orientation: <100>, <110>,<111>, off-oriented
• N type dopants: Arsenic, Phosphorus
• P type dopants: Boron
• Resistivity: From <0.001Ω·cm to >7000Ω·cm, engineered ultra high resistivity wafers for over 10kΩ·cm resistivity
• Thickness: 150mm: 400~1150µm; 200mm: 550~1150µm
Backside treatment: Etched, Polyback, LTO

• Growth method: Cz, MCz
• Diameter: 150mm, 200mm
• Crystal orientation: <100>, <110>,<111>, off-oriented
• N type dopants: Arsenic, Phosphorus
• P type dopants: Boron
• Resistivity: From <0.001Ω·cm to >7,000Ω·cm, engineered ultra high resistivity wafers for over 10kΩ·cm resistivity
• Thickness: 150mm: 380~1150µm; 200mm: 380~1150µm* (*Other thicknesses possible with certain limitations)
• Thickness tolerance: ±5µm (±3µm for demanding devices)
• TTV: <1µm
• Orientation accuracy: ±0.2° (±0.1° for demanding devices)

SOI refers to placing a thin layer of silicon on an insulating substrate. Transistors will be fabricated on a thin layer of silicon called "SOI". Devices based on SOI structures will essentially reduce junction capacitance and leakage current, increase switching speed, reduce power consumption, and achieve high-speed, low-power operation. As a next-generation silicon-based integrated circuit technology, SOI is widely used in most fields of microelectronics, and is also applied in other fields such as optoelectronics and MEMS. SOI wafers can be customerized as per the customer's request.

• CMOS, discrete devices, power devices, IGBT double layer epitaxy, SOI and buried layer epitaxy
• Wafer Diameter: 100mm, 125mm, 150mm, 200mm
• Monthly production capacity of more than 400,000 pieces (in terms of 4-inch epitaxial wafers)
• Epitaxial layer dopants: P, P+: Boron N, N+: Phosphorus, Arsine
• Epitaxial layer crystal orientation: <100>, <111>
• Epitaxial layer resistivity: P, N: 10^-1~10²Ω·cm (ASTM F723)
• Epitaxial layer resistivity central value deviation: ≤±5% (for 6-inch wafer)
• Epitaxial resistivity uniformity: ≤±3% (for 6-inch wafer)
• Epitaxial layer thickness: 1~100µm (ASTM F95, F110)
• Center value deviation of epitaxial layer thickness: ≤±5% (for 6-inch wafer)
• Epitaxial layer thickness uniformity: ≤±3% (for 6-inch wafer)
• Stacking fault density: 10/cm² (ASTM F1810)
• Customerized specifications accepted
• High-purity water cleaning service before and after processing

Ion implantation is an important process in the production of semiconductors. Implanter systems dope wafers with foreign atoms to modify material properties such as conductivity or crystal structure. The beam path is the center of an implanter system. Here the ions are generated, concentrated, greatly accelerated, and focused on the wafer at very high speeds. CETC components and spare parts made from high quality refractory metals etc. materials help to ensure that this process is as efficient, precise, and free of impurities as possible.
• Chambers (graphite, tungsten, molybdenum and alloys)
• Filaments (tungsten and tungsten alloys)
• Blades (graphite, tungsten, molybdenum and alloys)
• Brackets (tungsten, molybdenum and alloys)
• Cathodes (tungsten, molybdenum and alloys)
• Terminals (graphite)
• Analyzer parts (graphite)
• Insulators (ceramics)
• Spare parts (graphite, tungsten, molybdenum and alloys, ceramics, steel)
CETC supplies components and spare parts for over 100 ion implantation systems on the list below.
• AIBT: istar
• Applied Materials: 9000, 9200, 9200xR, 9500, 9500xR, Quantum, Quantum I, Quantum II, Quantum III, Quantum X, Quantum X+, Quantum xR, xR, xR/Leap, xR120, xR200, xR80
• Varian Semiconductor Equipment (now Applied Materials): VIISta Trident, PLAD, VIISta HCS, VIISta HCP +/I, VIISta 80, E1000, VIISion 200, VIISion 200+, VIISion 80+, VIISta HC, 120-10, 120XP, 160XP, 180XP, 80XP, VIISta 3000, Genus, Kestrel, VIISta 810 XE/XER, VIISta 900 XPT, VIISion, E220, E500, VIISta 810, VIISta 810 XE, VIISta 900, VIISta 900XP, 300D, 300XP, 350D
• Axcelis: GSD HC (200/200E/200E2), HC3, Ultra, Eterna, GSD 100, GSD 160A, GSD 200E, GSD 200E², GSD HC, GSD HC3, GSD III, GSD III LE, GSD LED, NV GSD, NV 10-160, NV 10-180, NV 10-80, Optima HD, ULE, Ultra, GSD HE, GSD VHE, GSD HE, GSD HE3, GSD VHE, Optima XE, Paradigm XE, NV 3206/3204, NV 6200, NV 8200, NV 8250, Optima MD
• Nissin: NH80, PR80, Exceed 3000, CLARIS, EXCEED2000A/2000AH, EXCEED2300AV, EXCEED3000AH, EXCEED9600A, NH20, NH45
• SEN: NV-GSD-160A, NV-GSD-80A, NV-GSDIII, NV-GSDIII-180, SD, NV-GSDIII-90E, NV-GSDIII-LE, NV-GSDIII-LE, V-GSD-HC, LEX, LEX3, SHX, NV-GSD-HE, NV-GSD-HE3, MC3MC3-II, NV-MC3
• Ulvac: IH-860, IDZ-7000, IDZ-8001, IDZ-9001, IM-200, IW-630

Chemical-mechanical polishing or planarization (CMP) is a key process to achieve global uniform planarization of wafers in the manufacturing process of integrated circuit chips, and chemical mechanical polishing fluid is the main chemical material used in the chemical mechanical polishing process. According to different polishing objects, CETC can supply chemical mechanical polishing liquids including copper and copper barrier layer polishing liquids, dielectric material polishing liquids, tungsten polishing liquids, cerium oxide abrasive-based polishing liquids, substrate polishing liquids, etc.
• Particle stability (Lower scratch)
• High mechanical polishing ability
• Dilutable
• High purity
• Colloidal Silica/KOH/NH3/... base

CETC supplies industry-standard polishing pad for chemical mechanical planarization (CMP). The CMP pad is made of a rigid, micro-porous polyurethane material. These properties enable the CMP pad to deliver localized planarization, excellent removal rates, low global non-uniformity and low defectivity. The CMP pad works effectively with slurries and conditioners to optimize CMP performance in tungsten, copper, ILD, STI, and polysilicon processes.
• Base material: Urethane
• Thickness (mm): 1.17~1.37
• Compressibility (%): 0.5~4.0
• Hardness (Shore-D): 52~62
• Specific Gravity (g/cm³): 0.77~0.83
• Applications: Berylium, germanium, indium phosphide, nickel, polysilicon, sapphire, silicon carbide, tungsten, zinc selenide, copper, ILD, STI

• Manufactured with high controlled diamond quality
• Suitable pad surface to meet customer's various requirements
• Excellent planarity
• Increase working diamond
• Minimize cut rate decay
• Longer conditioner life
• The scratch issue is resolved by the optimized quantity of working diamonds that will help to equalize the pressure towards diamonds

In plasma etching but also in coating processes (CVD, PVD) and in wet etching processes, the requirements of the semiconductor industry on quality are increasing continiously. As these spare parts are exposed to an aggressive and corrosive environment, they require special materials and a high grade of precision and purity. Even is these operating conditions, the components shouldn't generate any contamination or particles and their lifetime in the process has to be sufficient in order to keep expenses for maintenance and spare parts requirements within economical limits. CETC has the process-specific know-how for selecting the right material and manufacturing the corresponding components.
• Quartz (fused or synthetic in various qualities)
• Silicon (Monocryral, Multicrystal and Quasimonocrystal)
• Singlecrystal Silicon (Waferadapter)
• Ceramic (Oxideceramic, non-oxideceramic)
• CVD-SiC (Waferdummies)
• Other materials on demand

Parts made from CZ monocrystalline Silicon for high temperature processes, annealing and oxidation. For wafer diameters of 150 mm, 200 mm and 300 mm.
In the past furnace processes used almost exclusively wafer boats made from silicon carbide or quartz glass. Both materials have a different coefficient of expansion compared to the silicon wafer. This always causes friction on the back side of the wafer during the temperature processing, which then causes scratches and other defects.
Depending on the contact surface between the wafer and the boat and the process temperature, induced defects can under certain circumstances, be visible on the frontside of the wafer and hence can influence the yield of the chip in these regions. Defects on the backside of the wafer can at later processing be dislodged and redistributed on the frontside of adjacent wafers thus again causing a yield impact.
By using silicon boats (identical expansion coefficient to silicon wafers), this friction is prevented or sigficantly reduced.
The use of silicon boats significantly (proven by multiple evaluations) reduces the number of defects on the wafer backside. The same applies to the slip lines and imprints on the wafer front.
These technical improvements can lead to higher chip yields on the wafers, which has already been proven by several customers as part of successful product qualification.
Depending on the application / process, different designs of the boat contact area (where wafer contacts boat) may become necessary. CETC has experience with different applications and optimized design.
The silicon boats supplied by CETC are made exclusively from high-purity CZ monosilicon. By using the monosilicon with the identical purity of wafers, contamination (especially heavy metals) is prevented. After manufacturing, the boats are finally cleaned and packed in a class 100 clean room.

CETC provides o-rings, slit valve slides, KF/ISO/NW fittings, and endeffector-pads that are manufactured in cleanrooms and that creates less particles and metal contaminations. These enhanced material properties offer the following advantages:
• Longer lifetime
• Longer mean time between failure (MTBF)
• Less maintenance (wet cleaning and mechanical cleaning)
• Lower Cost of Ownership (CoO) caused by lower Cost of Consumables (CoC) and less maintenance